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M25PE80-VMN6TP 查看數據表(PDF) - STMicroelectronics

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M25PE80-VMN6TP Datasheet PDF : 61 Pages
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M25PE80
DC and AC parameters
Table 22.
AC characteristics (T9HX (0.11µm) Process, see Important note on page 6)(1)
Test conditions specified in Table 17 and Table 18
Symbol Alt.
Parameter
Min.
Typ.
Max. Unit
Clock Frequency for the following instructions:
fC
fC FAST_READ, RDLR, PW, PP, WRLR, PE, SE, D.C.
SSE, DP, RDP, WREN, WRDI, RDSR, WRSR
50 MHz
fR
Clock Frequency for READ instructions
D.C.
tCH(2) tCLH Clock High Time
9
tCL(2) tCLL Clock Low Time
9
Clock Slew Rate 2 (peak to peak)
0.1
33 MHz
ns
ns
V/ns
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tSHQZ(3)
tCLQV
tCLQX
tWHSL(4)
tSHWL(4)
tDP(3)
tRDP(3)
tW
tPW(5)
tPP(3)
tCSS S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
tDSU
tDH
Data In Setup Time
Data In Hold Time
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
tCSH
tDIS
tV
tHO
S Deselect Time
Output Disable Time
Clock Low to Output Valid
Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
S to Deep Power-down
S High to Standby Mode
Write Status Register Cycle Time
Page Write Cycle Time (256 Bytes)
Page Program Cycle Time (256 Bytes)
Page Program Cycle Time (n Bytes)
5
ns
5
ns
2
ns
5
ns
5
ns
5
ns
100
ns
8
ns
8
ns
0
ns
50
ns
100
ns
3
µs
30
µs
3
15 ms
11
23 ms
0.8
int(n/8) × 0.025(6)
3
ms
tPE
Page Erase Cycle Time
tSE
Sector Erase Cycle Time
tSSE
SubSector Erase Cycle Time
tBE
Bulk Erase Cycle Time
10
20 ms
1
5
s
40
150 ms
10
20
s
1. Preliminary data.
2. tCH + tCL must be greater than or equal to 1/ fC
3. Value guaranteed by characterization, not 100% tested in production.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence
including all the Bytes versus several sequences of only a few Bytes (1 n 256).
6. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
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