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M25PE80-VMN6TP 查看數據表(PDF) - STMicroelectronics

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M25PE80-VMN6TP Datasheet PDF : 61 Pages
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Revision history
M25PE80
Table 29. Document revision history
Date
Version
Changes
Important note on page 6 added.
VFQFPN8 and SO8W packages updated and SO8N (MN) package
added (see Section 12: Package mechanical).
Figure 4: Bus master and memory devices on the SPI bus updated and
explanatory paragraph added.
Reset signal behavior specified in Section 6.8: Read Lock Register
(RDLR), Section 6.10: Page Program (PP), Section 6.12: Page Erase
(PE) and Section 6.14: Sector Erase (SE) and Section 6.15: Bulk Erase
(BE). Section 8: Reset added, Table 23: Reset conditions modified and
Table 24: Timings after a Reset Low pulse added.
Table 3: Not for new design: TY7 process only, Software protection
scheme truth table (Sectors 0 and 15) applies to T7Y process only.
Software protection scheme figure removed. B3 and b2 apply to T7Y
process only in Table 8: Status Register format, Table 10: Lock Registers
30-Nov-2006
5
added, Table 11 applies to T7Y process only. Table 12: Lock Register In
added, Table 13 applies to T7Y process only.
Protection always prevails: applies to T7Y process only.
TLEAD added and VIO max changed in Table 16: Absolute maximum
ratings
M25PE80 products processed in T9HX process added to datasheet:
– WP pin replaces TSL (T7Y technology), see Section 2.6: Write Protect
(W) or Top Sector Lock (TSL)
Write Status Register (WRSR) and SubSector Erase (SSE) instructions
added for T9HX process
– subsector protection granularity removed in T9HX process, still exists in
T7Y process
Table 5: Memory organization updated to show subsectors
– Status Register BP2, BP1, BP0 bits and SRWD bit added.
SPM2 description and Table 4: Protected area sizes added in
Section 4.8: Protection modes.
15-Jan-2007
7
VFQFPN8 package specifications updated (see Table 25 and Figure 30).
small text changes.
60/61

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