M50FLW040AN5T 查看數據表（PDF） - STMicroelectronics
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M50FLW040AN5T
STMicroelectronics
M50FLW040AN5T Datasheet PDF : 52 Pages
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M50FLW040A, M50FLW040B
Table 5. Memory Identification Input Configuration (LPC mode)
Memory Number
ID2
ID1
ID0
A21
A20
A19
1 (Boot memory)
VIL or float VIL or float VIL or float
1
1
1
2
VIL or float VIL or float
VIH
1
1
0
3
VIL or float
VIH
VIL or float
1
0
1
4
VIL or float
VIH
VIH
1
0
0
5
VIH
VIL or float VIL or float
0
1
1
6
VIH
VIL or float
VIH
0
1
0
7
VIH
VIH
VIL or float
0
0
1
8
VIH
VIH
VIH
0
0
0
BUS OPERATIONS
The two interfaces, A/A Mux and FWH/LPC, sup-
port similar operations, but with different bus sig-
nals and timings. The Firmware Hub/Low Pin
Count (FWH/LPC) Interface offers full functional-
ity, while the Address/Address Multiplexed (A/A
Mux) Interface is orientated for erase and program
operations.
See the sections below, The Firmware Hub/Low
Pin Count (FWH/LPC) Bus Operations and Ad-
dress/Address Multiplexed (A/A Mux) Bus Opera-
tions, for details of the bus operations on each
interface.
Firmware Hub/Low Pin Count (FWH/LPC) Bus
Operations
The M50FLW040 automatically identifies the type
of FWH/LPC protocol from the first received nibble
(START nibble) and decodes the data that it re-
ceives afterwards, according to the chosen FWH
or LPC mode. The Firmware Hub/Low Pin Count
(FWH/LPC) Interface consists of four data signals
(FWH0/LAD0-FWH3/LAD3), one control line
(FWH4/LFRAME) and a clock (CLK).
Protection against accidental or malicious data
corruption is achieved using two additional signals
(TBL and WP). And two reset signals (RP and
INIT) are available to put the memory into a known
state.
The data, control and clock signals are designed
to be compatible with PCI electrical specifications.
The interface operates with clock speeds of up to
33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations are used to read
from the memory cells, specific registers in the
Command Interface or Firmware Hub/Low Pin
Count Registers. A valid Bus Read operation
starts on the rising edge of the Clock signal when
the Input Communication Frame, FWH4/
LFRAME, is Low, VIL, and the correct Start cycle
is present on FWH0/LAD0-FWH3/LAD3. On sub-
sequent clock cycles the Host will send to the
memory:
s ID Select, Address and other control bits on
FWH0-FWH3 in FWH mode.
s Type+Dir Address and other control bits on
LAD0-LAD3 in LPC mode.
The device responds by outputting Sync data until
the wait states have elapsed, followed by Data0-
Data3 and Data4-Data7.
See Table 6. and Table 8., and Figure 7. and Fig-
ure 9., for a description of the Field definitions for
each clock cycle of the transfer. See Table 26.,
and Figure 15., for details on the timings of the sig-
nals.
Bus Write. Bus Write operations are used to write
to the Command Interface or Firmware Hub/Low
Pin Count Registers. A valid Bus Write operation
starts on the rising edge of the Clock signal when
Input Communication Frame, FWH4/LFRAME, is
Low, VIL, and the correct Start cycle is present on
FWH0/LAD0-FWH3/LAD3. On subsequent Clock
cycles the Host will send to the memory:
s ID Select, Address, other control bits, Data0-
Data3 and Data4-Data7 on FWH0-FWH3 in
FWH mode.
s Cycle Type + Dir, Address, other control bits,
Data0-Data3 and Data4-Data7 on LAD0-
LAD3.
The device responds by outputting Sync data until
the wait states have elapsed.
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