M50FLW040AN5T 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

M50FLW040AN5T

4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory

STMicroelectronics 

M50FLW040A, M50FLW040B

Table 9. LPC Bus Write Field Definitions (1 Byte)

Clock Clock

Cycle Cycle

Number Count

Field

LAD0-

LAD3

Memory

I/O

Description

On the rising edge of CLK with LFRAME Low, the contents

1

1

START 0000b

I

of LAD0-LAD3 must be 0000b to indicate the start of a LPC

cycle.

CYCTY

Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1

2

1

PE +

011Xb

I

indicates the direction of transfer: 1b for write. Bit 0 is don’t

DIR

care (X).

3-10

8

ADDR

XXXX

A 32-bit address is transferred, with the most significant

I

nibble first. A23-A31 must be set to 1. A22=1 for memory

access, and A22=0 for register access. Table 5. shows the

appropriate values for A21-A19.

11-12

2

DATA

XXXX

I

Data transfer is two cycles, starting with the least significant

nibble.

13

1

TAR

1111b

I

The host drives LAD0-LAD3 to 1111b to indicate a

turnaround cycle.

14

1

TAR

1111b

(float)

O

The LPC Flash Memory takes control of LAD0-LAD3 during

this cycle.

15

1

SYNC

0000b

O

The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating it has received data or a command.

16

1

TAR

1111b

O

The LPC Flash Memory drives LAD0-LAD3 to 1111b,

indicating a turnaround cycle.

17

1

TAR

1111b

(float)

N/A

The LPC Flash Memory floats its outputs and the host takes

control of LAD0-LAD3.

Figure 10. LPC Bus Write Waveforms (1 Byte)

CLK

LFRAME

LAD0-LAD3

Number of

clock cycles

START

1

CYCTYPE

+ DIR

1

ADDR

8

DATA

2

TAR

2

SYNC

1

TAR

2

AI04430

Table 10. A/A Mux Bus Operations

Operation

G

W

RP

Bus Read

VIL

VIH

VIH

Bus Write

VIH

VIL

VIH

Output Disable

VIH

VIH

VIH

Reset

VIL or VIH

VIL or VIH

VIL

VPP

Don't Care

VCC or VPPH

Don't Care

Don't Care

DQ7-DQ0

Data Output

Data Input

Hi-Z

Hi-Z

17/52

Share Link: