Numonyx™ Wireless Flash Memory (W18)
Figure 19: Reset Operations Waveforms
(A) Reset during
read mode
VIH
RST# [P]
VIL
(B) Reset during
program or block erase
P1 ≤ P2
VIH
RST# [P]
VIL
(C) Reset during
program or block erase
P1 ≥ P2
VIH
RST# [P]
VIL
(D) VCC Power-up to
RST# high
VCC
VCC
0V
P1
R5
Abort
P2
R5
Complete
Abort
P2
R5
Complete
P3
7.4
AC I/O Test Conditions
Figure 20: AC Input/Output Reference Waveform
VCCQ
Input
0V
VCCQ/2
Test Points
VCCQ/2 Output
Note: Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed
conditions are when VCC = VCCMin.
Figure 21: Transient Equivalent Testing Load Circuit
VCCQ
R1
Device
Under Test
Out
CL
R2
Note: See Table 18 on page 43 for component values.
Datasheet
44
November 2007
Order Number: 290701-18