PIC16LC8X-04 查看數據表（PDF） - Microchip Technology
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PIC16LC8X-04 Datasheet PDF : 117 Pages
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PIC16C8X
8.3 Reset
The PIC16C8X differentiates between various kinds
of reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
Some registers are not affected in any reset condition;
their status is unknown on a POR reset and unchanged
in any other reset. Most other registers are reset to a
“reset state” on POR, MCLR or WDT reset during
normal operation and on MCLR reset during SLEEP.
They are not affected by a WDT reset during SLEEP,
since this reset is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared
differently in different reset situations (Table 8-6).
These bits are used in software to determine the nature
of the reset. Table 8-8 gives a full description of reset
states for all registers.
Figure 8-9 shows a simplified block diagram of the
on-chip reset circuit.
For all devices, except the PIC16C84, the MCLR reset
path has a noise filter to ignore small pulses. The
electrical specifications specifies the pulse width
requirements for the MCLR pin.
8.4 Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
8.4.1 POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will
eliminate external RC components usually needed to
create Power-on Reset. A minimum rise time for VDD
must be met for this to operate properly. See Electrical
Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be meet to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions
are met.
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting."
The POR circuit does not produce an internal reset
when VDD declines.
FIGURE 8-9: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT WDT
Module Time_Out
Reset
VDD rise
detect Power_on_Reset
S
VDD
OST/PWRT
OST
10-bit Ripple counter
R
OSC1/
CLKIN
PWRT
On-chip
RC OSC(1)
10-bit Ripple counter
Chip_Reset
Q
Note 1: This is a separate oscillator from the
RC oscillator of the CLKIN pin.
Enable PWRT
Enable OST
See Table 8-5
DS30081F-page 42
© 1995 Microchip Technology Inc.
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