PIC16LC8X-04 查看數據表（PDF） - Microchip Technology
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PIC16LC8X-04 Datasheet PDF : 117 Pages
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PIC16C8X
8.4.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from POR. The Power-up
Timer operates on an internal RC oscillator. The chip is
kept in reset as long as the PWRT is active. The PWRT
delay allows the VDD to rise to an acceptable level. A
configuration bit, PWRTE, can enable/disable the
PWRT (see Figure 8-1, Figure 8-2, and Figure 8-3 for
the operation of the PWRTE bit for a particular device).
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
8.4.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends. This ensures the crystal oscillator or
resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
8.4.4 TIME-OUT SEQUENCE
On power-up (Figure 8-10, Figure 8-11, and
Figure 8-12) the time-out sequence is as follows: First
PWRT time-out is invoked after a POR has expired.
Then the OST is activated. The total time-out will vary
based on oscillator configuration and PWRTE
configuration bit status. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
TABLE 8-5: TIME-OUT IN VARIOUS
SITUATIONS
Oscillator
Configuration
XT, HS, LP
RC
Power-up
PWRT
Enabled
PWRT
Disabled
72 ms + 1024TOSC
1024TOSC
72 ms
—
Wake-up
from
SLEEP
1024TOSC
—
Since the time-outs occur from the POR reset pulse, if
MCLR is kept low long enough, the time-outs will
expire. Then bringing MCLR high, execution will begin
immediately (Figure 8-11). This is useful for testing
purposes or to synchronize more than one PIC16CXX
device when operating in parallel.
Table 8-6 shows the significance of the TO and PD bits.
Table 8-7 lists the reset conditions for some special
registers, while Table 8-8 lists the reset conditions for
all the registers.
TABLE 8-6: STATUS BITS AND THEIR
SIGNIFICANCE
TO PD
Condition
1 1 Power-on Reset
0 x Illegal, TO is set on POR
x 0 Illegal, PD is set on POR
0 1 WDT Reset (during normal operation)
0 0 WDT Wake-up
1 1 MCLR Reset during normal operation
1 0 MCLR Reset during SLEEP or interrupt
wake-up from SLEEP
TABLE 8-7: RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Condition
Program Counter STATUS Register
Power-on Reset
000h
0001 1xxx
MCLR Reset during normal operation
000h
0001 1uuu
MCLR Reset during SLEEP
000h
0001 0uuu
WDT Reset (during normal operation)
000h
0000 1uuu
WDT Wake-up
PC + 1
uuu0 0uuu
Interrupt wake-up from SLEEP
PC + 1 (1)
uuu1 0uuu
Legend: u = unchanged, x = unknown.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
© 1995 Microchip Technology Inc.
DS30081F-page 43
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