PIC12F1822T-I/SL 查看數據表（PDF） - Microchip Technology

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PIC12F1822T-I/SL

8/14-Pin Flash Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC12F/LF1822/16F/LF1823

8.5.5 PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as

shown in Register 8-5.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0

R/W-0/0

R/W-0/0

R/W-0/0 R/W-0/0

U-0

U-0

OSFIF

C2IF(1)

C1IF

EEIF

BCL1IF

—

—

bit 7

U-0

—

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

C2IF: Comparator C2 Interrupt Flag bit(1)

1 = Interrupt is pending

0 = Interrupt is not pending

C1IF: Comparator C1 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

EEIF: EEPROM Write Completion Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

BCL1IF: MSSP Bus Collision Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

Unimplemented: Read as ‘0’

Note 1: PIC16F/LF1823 only.

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 93

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