PIC18LF1320-I/SOSQTP 查看數據表（PDF） - Microchip Technology

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PIC18LF1320-I/SOSQTP

18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F1220/1320

BTG

Bit Toggle f

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

[ label ] BTG f,b[,a]

0 ≤ f ≤ 255

0≤b<7

a ∈ [0,1]

(f<b>) → f<b>

None

0111 bbba ffff ffff

Bit ‘b’ in data memory location ‘f’ is

inverted. If ‘a’ is ‘0’, the Access Bank

will be selected, overriding the BSR

value. If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

1

Cycles:

1

Q Cycle Activity:

Q1

Q2

Decode

Read

register ‘f’

Q3

Process

Data

Q4

Write

register ‘f’

Example:

BTG

PORTB, 4

Before Instruction:

PORTB = 0111 0101 [0x75]

After Instruction:

PORTB = 0110 0101 [0x65]

BOV

Branch if Overflow

Syntax:

[ label ] BOV n

Operands:

-128 ≤ n ≤ 127

Operation:

if Overflow bit is ‘1’

(PC) + 2 + 2n → PC

Status Affected: None

Encoding:

1110 0100 nnnn nnnn

Description:

If the Overflow bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then

a two-cycle instruction.

Words:

1

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Decode

No

operation

If No Jump:

Read literal

‘n’

No

operation

Process

Data

No

operation

Write to PC

No

operation

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

Example:

HERE

Before Instruction

PC

=

After Instruction

If Overflow =

PC

=

If Overflow =

PC

=

BOV JUMP

address (HERE)

1;

address (JUMP)

0;

address (HERE + 2)

© 2007 Microchip Technology Inc.

DS39605F-page 205

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