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PIC18F45J50-I/SOSQTP 查看數據表(PDF) - Microchip Technology

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PIC18F45J50-I/SOSQTP Datasheet PDF : 562 Pages
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PIC18F46J50 FAMILY
EXAMPLE 19-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER (CONTINUED)
;
;DestBuf
;
;SrcBuf
;
udata
res
res
0x500
0x200
0x200
PrepareTransfer:
movlw
HIGH(DestBuf)
movwf
RXADDRH
movlw
LOW(DestBuf)
movwf
RXADDRL
movlw
movwf
movlw
movwf
HIGH(SrcBuf)
TXADDRH
LOW(SrcBuf)
TXADDRL
movlw
movwf
movlw
movwf
0x01
DMABCH
0xFF
DMABCL
BeginXfer:
bsf
DMACON1, DMAEN
;Execute whatever
;Somewhere else in our project, lets assume we have
;allocated some RAM for use as SPI receive and
;transmit buffers.
;Let’s reserve 0x500-0x6FF for use as our SPI
;receive data buffer in this example
;Lets reserve 0x700-0x8FF for use as our SPI
;transmit data buffer in this example
;Get high byte of DestBuf address (0x05)
;Load upper four bits of the RXADDR register
;Get low byte of the DestBuf address (0x00)
;Load lower eight bits of the RXADDR register
;Get high byte of SrcBuf address (0x07)
;Load upper four bits of the TXADDR register
;Get low byte of the SrcBuf address (0x00)
;Load lower eight bits of the TXADDR register
;Lets move 0x200 (512) bytes in one DMA xfer
;Load the upper two bits of DMABC register
;Actual bytes transferred is (DMABC + 1), so
;we load 0x01FF into DMABC to xfer 0x200 bytes
;The SPI DMA module will now begin transferring
;the data taken from SrcBuf, and will store
;received bytes into DestBuf.
;CPU is now free to do whatever it wants to
;and the DMA operation will continue without
;intervention, until it completes.
;When the transfer is complete, the SSP2IF flag in
;the PIR3 register will become set, and the DMAEN bit
;is automatically cleared by the hardware.
;The DestBuf (0x500-0x7FF) will contain the received
;data. To start another transfer, firmware will need
;to reinitialize RXADDR, TXADDR, DMABC and then
;set the DMAEN bit.
2011 Microchip Technology Inc.
DS39931D-page 287

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