PIC18F45J50-I/SOSQTP 查看數據表（PDF） - Microchip Technology

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PIC18F45J50-I/SOSQTP

28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC18F46J50 FAMILY

TABLE 30-31: A/D CONVERTER CHARACTERISTICS: PIC18F46J50 FAMILY (INDUSTRIAL)

Param

No.

Symbol

Characteristic

Min

Typ

Max Units

Conditions

A01 NR

Resolution

—

—

10

bit VREF  3.0V

A03 EIL

Integral Linearity Error

—

—

<±1

LSb VREF  3.0V

A04 EDL Differential Linearity Error

—

—

<±1

LSb VREF  3.0V

A06 EOFF Offset Error

—

—

<±3

LSb VREF  3.0V

A07 EGN Gain Error

—

—

<±3.5

LSb VREF  3.0V

A10

Monotonicity

Guaranteed(1)

— VSS  VAIN  VREF

A20 VREF Reference Voltage Range

(VREFH – VREFL)

2.0

—

3

—

—

V VDD  3.0V

—

V VDD  3.0V

A21 VREFH Reference Voltage High

VREFL

— VDD + 0.3V V

A22 VREFL Reference Voltage Low

VSS – 0.3V —

VREFH

V

A25 VAIN Analog Input Voltage

VREFL

—

VREFH

V

A30 ZAIN Recommended Impedance of

—

—

2.5

k

Analog Voltage Source

A50 IREF VREF Input Current(2)

—

—

5

A During VAIN acquisition.

—

—

150

A During A/D conversion

cycle.

Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

2: VREFH current is from RA3/AN3/VREF+/C1INB pin or VDD, whichever is selected as the VREFH source.

VREFL current is from the RA2/AN2/VREF-/CVREF/C2INB pin or VSS, whichever is selected as the VREFL source.

FIGURE 30-23: A/D CONVERSION TIMING

BSF ADCON0, GO

(Note 2)

131

Q4

130

A/D CLK

132

A/D DATA

9

8

7

...

...

2

1

0

ADRES

ADIF

GO

SAMPLE

OLD_DATA

SAMPLING STOPPED

NEW_DATA

TCY (Note 1)

DONE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

 2011 Microchip Technology Inc.

DS39931D-page 529

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