PSD511B1-C-90UI 查看數據表（PDF） - STMicroelectronics

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PSD511B1-C-90UI

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics 

Interrupt

Controller

(Cont.)

Interrupt Operation (cont.)

Interrupt Edge/Level Select Register

Bit 7

Bit 6

Bit 5

Bit 4

Sense7 Sense6 Sense5 Sense4

Bit 3

Sense3

Bit 2

Sense2

PSD5XX Family

Bit 1

Bit 0

Sense1 Sense0

Bits sense 0 ... sense 7 correspond to interrupt 0 ... interrupt 7.

When these bits are set to

1 = LEVEL sensitive

0 = EDGE sensitive (positive edge)

At RESET these bits initialize as 0 i.e., all interrupts come up as Edge sensitive.

Interrupt Read Clear Register

This is a read only register. Reading this register during initialization clears all the pending

edge sensitive interrupts.

Interrupt Request Latch Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ir 7

ir 6

ir 5

ir 4

ir 3

ir 2

ir 1

ir 0

Bits ir 0...ir 7 correspond to interrupt 0 ... interrupt 7.

When any of these bits are set by the interrupt controller to a “1”, the corresponding

Interrupt is pending service.

The MCU can read the interrupt request latch which shows the status of all interrupts. The

entire interrupt request latch can be cleared by reading the Interrupt Read Clear Register,

but Level sensitive interrupts cannot be cleared.

Interrupt Priority Status Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

*

*

*

*

NOTE: * = Reserved for future use, bits set to zero.

*

vect 2 vect 1 vect 0

The value of these 3 bits (vect2, vect1 and vect0) indicates the highest priority of the

interrupt to be serviced among multiple interrupts pending. Refer to the table above for

priorities of various interrupts. Reading this register clears the highest pending interrupt.

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