PSD511B1-C-90UI 查看數據表（PDF） - STMicroelectronics
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PSD511B1-C-90UI Datasheet PDF : 153 Pages
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PSD5XX Family
System
Configuration
(Cont.)
108
12.1 Reset Input
The reset input to the PSD5XX (RESET) is an active low signal which resets some of
the internal devices and configuration registers. The Timing Diagram in the AC/DC
characterization section shows the reset signal timing requirement. The active low range has
a minimum T1 duration. After the rising edge of RESET, the PSD5XX remains in
reset during T2 range. (See Figure 59). The PSD5XX must be reset at power up before it
can be used.
12.2 ZPLD and Memory During Reset
While the Reset Input is active, the ZPLD generates outputs as defined in the PSDabel
equations. The EPROM and SRAM blocks respond to the microcontroller bus cycle during
reset, but the data is not guaranteed.
12.3 Register Values During and After Reset
Table 34 summarizes the status of the volatile register values during and after reset. The
default values of the volatile registers are “0” after reset.
12.4 ZPLD Macrocell Initialization
The D flip flops in the macrocells in the GPLD can be cleared by:
t A product term (.RE) defined by the user, in PSDabel or
t The MACRO-RST (Reset) input, enabled and defined in PSDabel.
The Timer and Interrupt Controller macrocells in the PPLD are always cleared by the
Reset input.
Table 34. Registers Reset Values
Register Name
Device
Control
Port A, B, C, D, E
Data Out (data or address) Port A, B, C, D, E
Direction
Port A, B, C, D, E
Open Drain
Port C, D
Page Register
Page Logic
PMMR0, PMMR1
Power Management Unit
VM
Volatile Memory
DLCY
Timer
CMD0 – CMD3
Timer
Status Flags
Timer
Global Command
Timer
IMG0 – IMG3,
CNTR0 – CNTR3
Timer
Interrupt
Interrupt Controller
Reset State
Set to “0” (Address Out Mode)
Set to “0”
Set to “0” – Input Mode
Set to “0” – CMOS Outputs
Set to “0”
Set to “0”
Set to “0”
Set to “0”
Set to “0”, Clear
Set to “0”, Clear
Set to “0”, Clear
Undefined
Set to “0”, Disabled
Table 35. I/O Pin Status During Reset and Standby Mode
Port Configuration
Reset
Standby Mode
Port I/O
Input
Unchanged
ZPLD Output
Active
Depend on Inputs to the ZPLD
Address Out
Tri-stated
Not Defined
Data Port
Tri-stated
Tri-stated
Special Function Out
Tri-stated
Depending on Status of
Clock Input to the Counter/Timer
Peripheral I/O
Tri-stated
Tri-state
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