PSD5XX Family
AC/DC Parameters – ZPLD Timing Parameters (5 V ± 10% Versions)
Asynchronous Clock Mode (5 V ± 10% , Note 1)
Symbol
Parameter
Conditions
-70
-90**
-15
ZPLD_TURBO
Min Max Min Max Min Max OFF* Unit
Maximum Frequency
External Feedback
1/(tSA + tCOA)
26.32
25.00
21.74
f MAXA
Maximum Frequency
Internal Feedback
(fCNTA)
1/(tS A+ tCO A–10)
(Note 1)
Maximum Frequency
Pipelined Data
1/(tCH + tCL)
35.71
41.67
33.33
41.67
27.78
35.71
t SA
t HA
t CHA
t CLA
t COA
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output
Delay
Any Input
Any Input
Any Input
Any Input
Any Input
to Port B
8
8
12
8
8
12
12
12
15
12
12
15
30
32
37
Add 10
0
0
0
Add 10
t ARD
Array Delay for
Product Term
Expansion
Any Macrocell
16
18
22
0
tMINA Minimum Clock
Period
1/fCNT
28
30
43
0
NOTE: 1. Only Port B has asynchronous outputs. Clock into Macrocell Flip Flop is generated by a product term.
**If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters.
**The -90 speed is available only on Industrial Temperature Range product.
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
114