PSD501B1-C-90UI 查看數據表（PDF） - STMicroelectronics

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PSD501B1-C-90UI

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics 

PSD5XX Family

PSD5XX

Counter / Timer

Operation

(Cont.)

9.6.1 Counter/Timer Operation

There are four identical 16 bit Counter/Timers CNTR0,CNTR1,CNTR2 and CNTR3 and

associated Counter/Timer image registers IMG0,IMG1,IMG2 and IMG3. Refer to Table 21

for counter name and register correspondence. All Counter/Timers share a common clock

source. Each Counter/Timer can be operated in either WAVEFORM / PULSE mode or

EVENT COUNTER/TIME CAPTURE mode. Counter 2 can be set up as a Watchdog timer in

both modes. Note that in Event Counter/Time Capture mode COUNTER 2 can only be set

up as a Watch Dog Counter/Timer, whereas in the Waveform/Pulse mode Counter 2 can be

configured as a Pulse or Waveform generator or as a Watchdog timer. Refer to Table 24 for

possible combinations of Counter/Timer modes and refer to Figure 33 for additional details.

Each Counter/Timer can be controlled by an input pin or through a dedicated PPLD

macrocell output or by software. Counter/Timer outputs are available through port A or

port B pins in alternate function mode (Refer to the chapter on I/O ports). Polarity of

these inputs/outputs is software programmable. The following sections describe various

command and data registers that need to be initialized for proper function of these

Counter/Timers.

9.6.1.1 Counter/Timer Operating Modes

The PSD5XX Counter/Timer has five basic modes of operation: The Waveform and Pulse

or Event Counter, Time Capture, and Watchdog. The Waveform and Pulse modes cannot

be used in conjunction with Event and Time Capture modes. Both Waveform/Pulse or

Event Count/Time Capture modes can set Counter 2 into the fifth mode of operation, the

“WatchDog” mode.

The basic functional element used in all these modes is the Counter/Timer unit (CTU)

illustrated in Figure 33. This block consists of a 16 bit increment/decrement Counter, and a

16 bit image register with various control signals. The key function of the image register is

to enable microcontroller access of the Counter without asynchronously interrupting the

Counter. Software can configure each Counter/Timer using the associated Command

register. The Counter/Timer of the PSD5XX employs four CTUs to realize the various

modes of operation.

Table 21. Registers Used By Counters

Counter Name

Counting Register

Counter 0

CNTR0

Counter 1

CNTR1

Counter 2

CNTR2

Counter 3

CNTR3

Image Register

IMG0

IMG1

IMG2

IMG3

66

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