ST7MC2N6T3 查看數據表（PDF） - STMicroelectronics

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ST7MC2N6T3

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION

CPU CC REGISTER INTERRUPT BITS

Read / Write

Reset Value: 111x 1010 (xAh)

7

0

1

1

I1

H

I0

N

Z

C

Bit 5, 3 = I1, I0 Software Interrupt Priority

These two bits indicate the current interrupt soft-

ware priority.

Interrupt Software Priority Level I1

I0

Level 0 (main)

Low

1

0

Level 1

0

1

Level 2

0

0

Level 3 (= interrupt disable*) High 1

1

These two bits are set/cleared by hardware when

entering in interrupt. The loaded value is given by

the corresponding bits in the interrupt software pri-

ority registers (ISPRx).

They can be also set/cleared by software with the

RIM, SIM, HALT, WFI, IRET and PUSH/POP in-

structions (see “Interrupt Dedicated Instruction

Set” table).

*Note: MCES, TRAP and RESET events can in-

terrupt a level 3 program.

INTERRUPT SOFTWARE PRIORITY REGIS-

TERS (ISPRX)

Read/Write (bit 7:4 of ISPR3 are read only)

Reset Value: 1111 1111 (FFh)

7

0

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

These four registers contain the interrupt software

priority of each interrupt vector.

– Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where

its own software priority is stored. This corre-

spondence is shown in the following table.

Vector address

FFFBh-FFFAh

FFF9h-FFF8h

...

FFE1h-FFE0h

ISPRx bits

I1_0 and I0_0 bits*

I1_1 and I0_1 bits

...

I1_13 and I0_13 bits

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits

in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (ex-

ample: previous=CFh, write=64h, result=44h)

The RESET, TRAP and MCES vectors have no

software priorities. When one is serviced, the I1

and I0 bits of the CC register are both set.

*Note: Bits in the ISPRx registers which corre-

spond to the MCES can be read and written but

they are not significant in the interrupt process

management.

Caution: If the I1_x and I0_x bits are modified

while the interrupt x is executed the following be-

haviour has to be considered: If the interrupt x is

still pending (new interrupt or flag not cleared) and

the new software priority is higher than the previ-

ous one, the interrupt x is re-entered. Otherwise,

the software priority stays unchanged up to the

next interrupt request (after the IRET of the inter-

rupt x).

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