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ST7MC2N6T3 查看數據表(PDF) - STMicroelectronics

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ST7MC2N6T3 Datasheet PDF : 309 Pages
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ST7MC1xx/ST7MC2xx
EXTERNAL INTERRUPT CONTROL REGISTER (EICR) (Cont’d)
- ei0 (port D6..4)
IS31 IS30
00
01
External Interrupt Sensitivity
IPA bit =0
Falling edge &
low level
Rising edge only
IPA bit =1
Rising edge
& high level
Falling edge only
Bit 0 = IPA Interrupt polarity for port D
This bit is used to invert the sensitivity of the port D
[6:4] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
1 0 Falling edge only Rising edge only
11
Rising and falling edge
- ei0 (port D3..1)
IS31 IS30
00
01
10
11
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
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