STA321MPL 查看數據表（PDF） - STMicroelectronics

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STA321MPL

Scalable digital microphone processor

STMicroelectronics 

I2C bus operation

STA321MP

address and if a match is found, it acknowledges the identification on SDA bus during the

9th-bit time. The byte following the device identification byte is the internal space address.

5.3

5.3.1

5.3.2

Write operation

Following the START condition the master sends a device select code with the RW bit set

to 0. The STA321MP acknowledges this and then waits for the byte of internal address.

After receiving the internal byte address the STA321MP again responds with an

acknowledgement.

Byte write

In the byte write mode the master sends one data byte, which is acknowledged by the FFX

core. The master then terminates the transfer by generating a STOP condition.

Multi-byte write

The multi-byte write modes can start from any internal address. The master generating a

STOP condition terminates the transfer.

Figure 4. Write mode sequence

BYTE

WRITE

START

MULTIBYTE

WRITE

START

DEV-ADDR

DEV-ADDR

ACK

RW

ACK

RW

SUB-ADDR

ACK

SUB-ADDR

ACK

DATA IN

DATA IN

ACK

STOP

ACK

DATA IN

ACK

STOP

AM045330v1

Figure 5. Read mode sequence

CURRENT

ADDRESS

READ

START

RANDOM

ADDRESS

READ

START

SEQUENTIAL

CURRENT

READ

START

SEQUENTIAL

RANDOM

READ

START

ACK

DEV-ADDR

DEV-ADDR

RW

ACK

DEV-ADDR

RW

RW= ACK

HIGH

DEV-ADDR

ACK

RW

DATA

SUB-ADDR

DATA

NO ACK

STOP

ACK

DEV-ADDR

START

ACK

DATA

ACK

RW

ACK

SUB-ADDR

ACK

START

DEV-ADDR

ACK

RW

DATA

DATA

DATA

NO ACK

STOP

NO ACK

ACK

STOP

DATA

ACK

DATA

NO ACK

STOP

AM045331v1

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Doc ID 022647 Rev 1

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