STA321MPL 查看數據表（PDF） - STMicroelectronics

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STA321MPL

Scalable digital microphone processor

STMicroelectronics 

STA321MP

Registers

7.2

7.2.1

Register description

Configuration register A (0x00)

D7

COS1

1

D6

COS0

0

D5

DSPB

0

D4

IR1

0

D3

IR0

0

D2

MCS2

0

D1

MCS1

1

D0

MCS0

1

Bit

RW

RST

Name

Description

0

RW

1

1

RW

1

2

RW

0

MCS0

MCS1

MCS2

Master clock select: selects the ratio between the

input sampling frequency (PDM I/FCLK) and the

input clock(XTI).

The STA321MP supports a sampling rate of 2.8224 MHz. Therefore the internal clock is:

● 90.3168 MHz for the respective sampling frequency

The external clock frequency provided to the XTI pin must be a multiple of the input

sampling frequency (fs). The relationship between the input clock and the input sampling

rate is determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits

determine the PLL factor generating the internal clock and the IRn bits determine the

oversampling ratio used internally.

Input sampling rate

IR

fs (kHz)

PDM I/F 2822.4

11

Interpolation ratio select

1XX

2 * fs

011

4 * fs

MCS[2:0]

010

6 * fs

001

8 * fs

000

10 * fs

Bit RW

3

RW

4

RW

RST

Name

0

IR0

0

IR1

Description

Interpolation ratio select: selects the internal

interpolation ratio based on the input sampling

frequency

The STA321MP has variable interpolation (oversampling) settings such that internal

processing and FFX output rates remain consistent. The first processing block interpolates

by either 4 times, 2 times, or 1 time (pass-through).

The oversampling ratio of this interpolation is determined by the IR bits.

I

IR[1,0]

11

Input sampling rate

Fs (kHz)

2822.4

1st stage interpolation ratio

PDM CLK to 176.4 kHz conversion

Doc ID 022647 Rev 1

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