STA321MPL 查看數據表（PDF） - STMicroelectronics
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STA321MPL Datasheet PDF : 50 Pages
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Registers
STA321MP
7.2.3 Configuration register E (0x04)
7.2.4
D7
C8BO
0
D6
C7BO
0
D5
C6BO
0
D4
C5BO
0
D3
C4BO
0
D2
C3BO
0
D1
C2BO
0
D0
C1BO
0
Bit RW RST
Name
Description
0
RW
0
1
RW
0
2
RW
0
3
RW
0
4
RW
0
5
RW
0
6
RW
0
7
RW
0
C1BO
C2BO
C3BO
C4BO
C5BO
C6BO
C7BO
C8BO
Channels 1, 2, 3, 4, 5, 6, 7, and 8 binary output
mode enable bits. A setting of 0 indicates ordinary
FFX tristate output. A setting of 1 indicates binary
output mode.
Each individual channel output can be set to output a binary PWM stream. In this mode
output A of a channel will be considered the positive output and output B is the negative
inverse.
Configuration register F (0x05)
D7
PWMS2
0
D6
PWMS1
0
D5
PWMS0
0
D4
BQL
0
D3
PSL
0
D2
DEMP
0
D1
DRC
0
D0
HPB
0
Bit RW RST
Name
Description
0
RW
0
HPB
High-pass filter bypass bit: a setting of 1 bypasses
the internal AC coupling digital high-pass filter
The STA321MP features an internal digital high-pass filter for the purpose of AC coupling.
The purpose of this filter is to prevent DC signals from passing through an FFX amplifier. DC
signals can cause speaker damage.
If HPB = 1, then the filter that the high-pass filter utilizes is made available as user-
programmable biquad#1.
Bit RW RST
Name
Description
1
RW
0
DRC
Dynamic range compression/anti-clipping
0: limiters act in anti-clipping mode
1: limiters act in dynamic range compression mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression.
When used in anti-clipping mode, the limiter threshold values are constant and dependent
on the limiter settings.
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Doc ID 022647 Rev 1
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