DSM2190F4 查看數據表（PDF） - STMicroelectronics
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DSM2190F4
STMicroelectronics
DSM2190F4 Datasheet PDF : 61 Pages
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DSM2190F4
Table 28. CPLD Macrocell Synchronous Clock Mode Timing
Symbol
Parameter
Conditions
-15
Min
Max
Maximum Frequency
External Feedback
1/(tS+tCO)
18.8
fMAX
Maximum Frequency
Internal Feedback (fCNT)
1/(tS+tCO–10)
23.2
Maximum Frequency
Pipelined Data
1/(tCH+tCL)
33.3
tS
Input Setup Time
25
tH
Input Hold Time
0
tCH
Clock High Time
Clock Input
15
tCL
Clock Low Time
Clock Input
15
tCO
Clock to Output Delay
Clock Input
28
tARD
CPLD Array Delay
Any Macrocell
29
tMIN
Minimum Clock Period2
tCH+tCL
29
Note: 1. Fast Slew Rate output available on PB3-PB0, and PD2-PD0.
2. CLKIN (PD1) tCLCL = tCH + tCL .
Table 29. CPLD Macrocell Asynchronous Clock Mode Timing
Symbol
Parameter
Conditions
-15
Min
Max
Maximum Frequency
External Feedback
1/(tSA+tCOA)
19.2
fMAXA
Maximum Frequency
Internal Feedback (fCNTA)
1/(tSA+tCOA–10)
23.8
Maximum Frequency
Pipelined Data
1/(tCHA+tCLA)
27
tSA
Input Setup Time
12
tHA
Input Hold Time
15
tCHA
Clock High Time
22
tCLA
Clock Low Time
15
tCOA
Clock to Output Delay
40
tARD
CPLD Array Delay
Any Macrocell
29
tMINA
Minimum Clock Period
1/fCNTA
42
PT
Aloc
Turbo
Off
Slew
Rate1
Unit
MHz
MHz
MHz
Add 4 Add 20
ns
ns
ns
ns
Sub 6 ns
Add 4
ns
ns
PT
Aloc
Turbo
Off
Slew
Rate
Unit
MHz
MHz
MHz
Add 4 Add 20
ns
ns
Add 20
ns
Add 20
ns
Add 20 Sub 6 ns
Add 4
ns
ns
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