LTC1645CS 查看數據表（PDF） - Linear Technology

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LTC1645CS

Dual-Channel Hot Swap Controller/Power Sequencer

Linear Technology 

LTC1645

APPLICATIO S I FOR ATIO

voltage on the external capacitor CTIMER starts to ramp up

with a slope dv/dt = 2µA/CTIMER. When the voltage reaches

the trip point (1.23V), the timer is reset by pulling the

TIMER pin back to ground. The timer period is

t = (1.23V • CTIMER)/2µA. For a 200ms delay, use a 0.33µF

capacitor.

Electronic Circuit Breaker

The LTC1645 features an electronic circuit breaker func-

tion that protects against short circuits or excessive out-

put currents. By placing sense resistors between the

supply inputs and sense pins of the supplies, the circuit

breaker trips whenever the voltage across either sense

resistor is greater than 50mV for more than 1.5µs. If the

circuit breaker trips, both GATE pins are immediately

pulled to ground and the external N-channels FETs are

quickly turned off (time point 6 in Figure 12). The circuit

breaker resets and another timing cycle starts by taking

CURRENT

RAMPING UP FAULT

RESET FAULT

AND RAMP UP

VCCn

12 3 4 5 6

7 8 9 10

ON

VCCn – VSENSEn

TIMER

GATEn

the ON pin below 0.4V and then high as shown at time

point 7.

At the end of the timer cycle (time point 8), the charge

pump turns on again. If the circuit breaker feature is not

required, short the SENSEn pin to VCCn.

If the 1.5µs response time is too fast to reject supply noise,

add external resistors and capacitors RF and CF to the

sense circuit as shown in Figure 13.

The ON Pin

The ON pin is used to control system operation as shown

in Figure 14. At time point 1, the board makes connection

and the supplies power up the chip. At time point 2, the ON

pin goes high and a timer cycle starts as long as both VCC

pins are higher than the undervoltage lockout trip point

(2.23V for VCC1 and 1.12V for VCC2) and an overcurrent

fault is not detected. At the end of the timer cycle (time

point 3), the charge pump is turned on and the GATEn pin

voltages start to ramp up with the output supply voltages,

VOUTn, following one gate-to-source voltage drop lower.

At time point 4, VOUT2 reaches its power-good trip level

(this example assumes the FB pin resistive divider is

connected to VOUT2) and a timing cycle starts. At the end

of the timing cycle (time point 5), RESET goes high and the

power-up process is complete.

RAMPING UP AND

DOWN TOGETHER

RAMPING UP AND

DOWN SEPARATELY

RAMPING UP AND

TURNING OFF FAST

12 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20

VOUTn

VCCn

RESET

1645 F12

Figure 12. Current Fault Timing

2V

ON

0.8V

0.4V

0V

TIMER

GATE1

RF

CF

VOUT1

VCCn SENSEn GATEn

LTC1645

GATE2

VOUT2

1645 G13

RESET

1645 F14

Figure 13. Extending the Short-Circuit Protection Delay

Figure 14. ON Pin Waveforms

13

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