LTC1645CS 查看數據表（PDF） - Linear Technology

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LTC1645CS

Dual-Channel Hot Swap Controller/Power Sequencer

Linear Technology 

LTC1645

APPLICATIO S I FOR ATIO

Switching Regulator Supply Sequencing

Figure 21 shows the LTC1645 sequencing two power

supplies, the lower of which is generated by the LTC1430A

switching regulator. Connecting the regulator’s FB pin

resistor divider (R1 and R2) to the other side of the pass

FET (Q1) allows the LTC1430A to compensate for the

voltage drop across RSENSE1 and Q1, assuring an accurate

voltage output. The spare comparator holds the LTC1645’s

ON pin low until the LTC1430A’s output is at least 3V, and

shuts both channels off if it drops below 3V. When the

ON/OFF signal is taken high to 5V (turn-on), the voltage at

the ON pin rises with an RC exponential characteristic,

reaching 0.8V first. This starts a timing cycle, and GATE1

begins to rise. GATE2 starts to ramp up after the ON pin

reaches 2V. As long as the timing cycle is shorter than the

time for the ON pin to rise from 0.8V to 2V, VOUT2 ramps

up after VOUT1. RESET goes high one timing cycle after

VOUT1 exceeds 3V. When the ON/OFF signal is brought

low, the voltage at the ON pin exponentially decays and

GATE2 ramps down before GATE1. RESET goes low as

soon as VOUT1 falls below 3V. Figure 22 shows the power-

up and power-down sequences of the circuit in Figure 21.

Switching Regulator Hot Swapping

High current switching regulators usually require large

bypass capacitors on both input and output for proper

operation. The application in Figure 23 controls the inrush

current to the LTC1649’s input bypass capacitors and

ramps the two output voltages up and down together. As

with the previous application, connecting the regulator’s

FB pin resistor divider to the other side of the output pass

FET (Q2) allows the LTC1649 to compensate for the

voltage drop across Q2, assuring an accurate voltage

output. The voltage at the LTC1645’s ON pin reaches 0.8V

when VIN exceeds 3V, and GATE1 begins to ramp up one

timing cycle later. As the regulator’s output rises, D2 pulls

the ON pin above 2V and GATE2 begins to rise, ramping

VOUT1 and VOUT2 up together. RESET goes high one timing

cycle after VOUT1 exceeds 3V and VOUT2 exceeds 2.35V.

Figure 24 shows the circuit in Figure 23 powering up.

Care should be taken connecting a switching regulator’s

FB or SENSE pins to a node other than its output. Depend-

ing on the regulator’s internal architecture, unusual be-

havior may occur as it tries in vain to raise the voltage at

ON

2V/DIV

VREGOUT

2V/DIV

VOUT1

2V/DIV

VOUT2

2V/DIV

RESET

5V/DIV

Figure 22. Switching Regulator Supply Sequencing

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