Z8018010PSC 查看數據表（PDF） - Zilog

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Z8018010PSC

ENHANCED Z180 MICROPROCESSOR

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Z80180/Z8S180/Z8L180

Enhanced Z180 Microprocessor

ASCI TIME CONSTANT REGISTERS

If the SS2-0 bits of the CNTLA register are not 111, and the

BRG Mode bit in the ASEXT register is 1, the ASCI divides

the PHI clock by twice (the 16-bit value in these registers,

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plus two), to obtain the clock that is presented to the trans-

mitter and receiver for division by 1, 16, or 64 and that can

be output on the CKA1 pin.

ASCI Time Constant Register 0 Low (ASTCOL, I/O Address IAH)

ASCI Time Constant Register 1 Low (ASTCIL), I/O Address ICH)

Bit

7

6

5

4

3

2

1

0

LS 8 Bits of Time Constant

ASCI Time Constant Register 0 High (ASTCOH, I/O Address IBH)

ASCI Time Constant Register 1 High (ASTCIH), I/O Address IDH)

Bit

7

6

5

4

3

2

1

0

MS 8 Bits of Time Constant

Figure 53. ASCI Time Constant Registers

1-48

PRELIMINARY

DS971800401

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