Z8018010PSC 查看數據表（PDF） - Zilog

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Z8018010PSC

ENHANCED Z180 MICROPROCESSOR

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Z80180/Z8S180/Z8L180

Enhanced Z180 Microprocessor

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DMA SOURCE ADDRESS REGISTER CHANNEL 0

(SAR0: I/O Address = 20H to 22H) specifies the physical source address for channel 0 transfers. The register contains

20 bits and can specify up to 1024 KB memory addresses or up to 64 KB I/O addresses. Channel 0 source can be mem-

ory, I/O, or memory mapped I/O. For I/O, the MS bits of this register identify the Request Handshake signal.

DMA Source Address Register, Channel 0L

Mnemonic SAR0L

DMA Source Address Register Channel 0B

Mnemonics SAR0B

Address 20

Address 22

76 54 32 1 0

-- -- -- -- -- -- -- --

DMA Channel 0 Address

Figure 55. DMA Source Address Register 0L

DMA Source Address Register, Channel 0H

Mnemonic SAR0H

Address 21

76 54 32 1 0

-- -- -- -- -- -- -- --

DMA Channel B Address

Figure 57. DMA Source Address Register 0B

76 54 32 1 0

-- -- -- -- -- -- -- --

DMA Channel 0 Address

Figure 56. DMA Source Address Register 0H

1-50

PRELIMINARY

DS971800401

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