Z8018010PSC 查看數據表（PDF） - Zilog

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Z8018010PSC

ENHANCED Z180 MICROPROCESSOR

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Z80180/Z8S180/Z8L180

Enhanced Z180 Microprocessor

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DMA BYTE COUNT REGISTER CHANNEL 0

(BCRO: I/O Address = 26H to 27H) specifies the number of bytes to be transferred. This register contains 16 bits and may

specify up to 64 KB transfers. When one byte is transferred, the register is decremented by one. If “n” bytes should be

transferred, “n” must be stored before the DMA operation.

Note: All DMA Count Register channels are undefined during reset.

DMA Byte Count Register Channel 0L

Mnemonic BCR0L

DMA Byte Count Register Channel 1L

Mnemonic BCR1L

Address 26

Address 2E

Figure 61. DMA Byte Count Register 0L

DMA Byte Count Register Channel 0H

Mnemonic BCR0H

Address 27

Figure 63. DMA Byte Count Register 1L

DMA Byte Count Register Channel 0H

Mnemonic BCR1H

Address 2F

Figure 62. DMA Byte Count Register 0H

Figure 64. DMA Byte Count Register 0H

1-52

PRELIMINARY

DS971800401

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