CS48500 查看數據表（PDF） - Cirrus Logic
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CS48500 Datasheet PDF : 28 Pages
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CS48500 Data Sheet
32-bit Audio Decoder DSP Family
5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode
Parameter
SCP_CLK frequency1
SCP_CLK low time
SCP_CLK high time
SCP_SCK rising to SCP_SDA rising or falling for
START or STOP condition
Symbol
fiicck
tiicckl
tiicckh
tiicckcmd
Min
-
1.25
1.25
1.25
Typical
Max
Units
400
kHz
-
µs
-
µs
µs
START condition to SCP_CLK falling
tiicstscl 1.25
-
µs
SCP_CLK falling to STOP condition
tiicstp
2.5
-
µs
Bus free time between STOP and START conditions tiicbft
3
-
µs
T Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100
ns
F Hold time SCP_SDA input after SCP_CLK falling
tiich
20
-
ns
SCP_CLK low to SCP_SDA out valid
tiicdov
-
18
ns
A SCP_CLK falling to SCP_IRQ# rising
tiicirqh
-
3*DCLKP + 40 ns
NAK condition to SCP_IRQ# low
tiicirql
3*DCLKP + 20
ns
R SCP_CLK rising to SCB_BSY# low
tiicbsyl
- 3*DCLKP + 20
ns
D 1.The specification fiicck indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the firmware applica-
tion. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data
buffer.
IAL HI tiicckcmd
tiicckl
tiicr
tiicf
tiicckcmd
NT LP SCP_CLK
E E tiicstscl
0
1
6
7
8
01
6
tiicckh
tiicdov
fiicck
7
8
tiicstp
tiicbft
ID D SCP_SDA
F SCP_IRQ#
A6
tiicsu
tiich
A0 R/W ACK MSB
tiicirqh
LSB
ACK
tiicirql
N tiiccbsyl
CO SCP_BSY#
Figure 5. Serial Control Port - I2C Slave Mode Timing
18
©Copyright 2006 Cirrus Logic, Inc.
DS734A3
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