ML6430CH 查看數據表（PDF） - Micro Linear Corporation

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ML6430CH

Genlocking Sync Generator with Digital Audio Clock for NTSC, PAL & VGA

Micro Linear Corporation 

ML6430/ML6431

FUNCTIONAL DESCRIPTION (Continued)

SERIAL BUS OPERATION

The serial bus control in the ML6430/ML6431 has two

levels of addressing: Device Addressing and Register

Addressing.

Device Addressing: Figure 5 shows the physical

waveforms generated in order to address the ML6430/

ML6431. There are six basic parts of the waveform:

1. Start Indication: Clock Cycle 0

2. Device Address Shifted: Clock Cycle 1 through 8

3. Device Address Strobed and Decoded: Clock Cycle 9

4. Data Shifted : Clock Cycle 10 through 17

5. Data Strobed into Appropriate Register: Clock Cycle 18

6. Stop indication: Clock Cycle 19

Register Addressing: Figure 6 shows the register map of

the ML6430/6431. There are two basic parts of each

received data byte: Address Nibble and Data Nibble

1. Address Nibble: The upper 4 bits of the data byte

gives the register number in which to place the

data.

2. Data Nibble: The lower 4 bits of the data byte is

the data to be placed in the currently addressed

register nibble.

SDATA

START

tRISE

tSET/START

SCLK

All Other SDATA Transitions Must Occur While SCLK is Low

START: A Falling Edge on the SDATA While SCLK is Held High

STOP: A Rising Edge on the SDATA While SCLK is Held High

tFALL

Figure 5. Definition of START & STOP on Serial Data Bus

STOP

SDATA

SCLK

0

MSB

A7

A6

1

2

A1

A0

7

8

9

MSB

D7

D6

10

11

D1

D0

16

17

18

STOP

22

SCLK:

SCLK:

SDATA:

SCLK:

SCLK:

SDATA:

SCLK:

SDATA;

9th pulse strobes address decoder

Rising edge enables data transfer

Value set to A6, Device Address (MSB-1)

Falling edge disables data transfer

Rising edge enables data transfer

Value set to A7, Device Address MSB

Falling edge in prep for first address transfer

Falling edge with SCLK Hi means start of sequence

SDATA:

SDATA:

SCLK:

SCLK:

SDATA:

SCLK:

SCLK:

SDATA:

Rising edge with SCLK Hi = STOP

Value set low in prep for STOP

18th pulse strobes data shift register

Rising edge enables data transfer

Value set to D6, Data MSB-1

Falling edge disables data transfer

Rising edge enables data transfer

Value set to D7, Data MSB

Figure 6. Definition of DATA FORMAT on Serial Data Bus

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