ML6430CH 查看數據表（PDF） - Micro Linear Corporation

零件编号

产品描述 (功能)

生产厂家

ML6430CH

Genlocking Sync Generator with Digital Audio Clock for NTSC, PAL & VGA

Micro Linear Corporation 

ML6430/ML6431

SDATA

SCLK

0

‘1’

‘0’ ‘1’ ‘1’ ‘0’

‘0’ ‘1’ ‘0’

Ø

R3 R2 R1 R0 D3 D2 D1 D0

DEVICE ADDR = ‘B2’

REGISTER

SUB-ADDR

DATA

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

G

H

STROBE

Ø

I

SCLK: Address decode strobed on 9th clock

[Data is ‘don’t care’ during strobe]

SDATA: ‘1011 0010’ shifted on next 8 clocks

SCLK: Falling edge in prep for device address transfer

SDATA:

SDATA:

SDATA:

Final Clock strobes data into register

Second 4 bits are Register Data

First 4 bits are Register Address

Figure 7. Typical Serial Bus Command

SDATA

10 1

1

0

01

0

0 1 1 10 1

0

0

SCLK

START

1 2 3 4 5 6 7 8 9 A B CD E F G H

I

STOP

Device Address

Register Address

Strobe in Address

Data

Data Strobed into

Appropriate Register

Figure 8. Serial Bus Command to Set Bit #2 in Register 7

23

Share Link: