FBFM2112F897CSLJLS 查看數據表（PDF） - Intel

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FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.5.1

BOOT FSM:

SWITCH MGMT:

PORT MGMT:

LED CTRL:

The bootstrap finite state machine. This is activated once at

startup to setup internal registers, repair internal RAM and

initialize memory.

Interface to manage the switch, this include setting up any

frame control registers, access to global statistics and accessing

the lookup table.

Interface to manage the port.

A block that retrieves the status of the port and present it to a

serial LED interface.

Logical CPU Interface

{Described in Table 73 through Table 76}

The FM2112 supports packet transmission to any port of the switch and

reception from any port of the switch to the local CPU controller

through the CPU Interface. However, this interface is a slave only bus

interface. There is no built in DMA controller to retrieve packets from

memory for transmission or forward packets received to internal

memory. Packet transmission and reception requires the CPU Interface

master to write or read each word of a packet transmitted or received.

The FM2112 provides DMA signals allowing the usage of an external

dual-channel DMA controller to do the data transfer for the CPU. This is

shown in Figure 13.

54

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