FBFM2112F897CSLJLS 查看數據表（PDF） - Intel

零件编号

产品描述 (功能)

生产厂家

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.5.2

3.5.2.1

3.5.2.2

3.5.2.3

3.5.2.4

• If the CRC is enabled then packets transferred from the CPU to the switch do not

require a valid CRC. In this case the last four bytes are overwritten with a valid CRC

(note: the packet data transmission must include space for the CRC).

• If CRC generation is not enabled, then it is a requirement of software to generate a

valid CRC.

• The CRC is not used to check data integrity in the transmission from CPU to the

switch. There is a parity check in the CPU Interface for transmission from the CPU

to the switch.

Bootstrap Finite State Machine

{Described in registers Table 36}

The BOOT FSM is normally the initial chip manager.

If the AUTOBOOT signal is asserted, then the BOOT FSM starts

automatically after RESET is de-asserted, initializing the chip according

to the content of fusebox and returning control to the CPU Interface

after the initialization is completed.

If the AUTOBOOT signal is de-asserted, then the BOOT FSM will only

start if the CPU forces it to start. The CPU in this case will indicate

which phases shall be executed. It is not possible to change order, it is

only possible to either execute one phase or skip over that phase.

Starting the BOOT FSM and defining which phase is executed is

controlled by the CHIP_MODE register.

The BOOT FSM can go through 3 phases: FUSEBOX processing, RAM

initialization, EEPROM processing.

Boot Phase 1 - Fusebox

During this phase, the BOOT FSM read the fusebox and stores the value

read into the FUSEBOX CSRs.

Boot Phase 2 - Memory initialization

During this phase, the BOOT FSM initializes the memory to default

values and also initializes the list of pointers in the scheduler.

Boot Phase 3 - EEPROM Read

Chip Bring-up without EEPROM

EEPROM operations will be started if the EEPROM_ENABLED pin-strap is

set.

The SPI FSM will issue one read command to address 24'd0 - the

EEPROM will continue to auto-increment through all of its memory. The

BOOT FSM will be able to stall the SPI FSM in -order to give time to any

required fusebox operations.

61

Share Link: