FBFM2112F897CSLJLS 查看數據表（PDF） - Intel

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FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.6

3.6.1

Notes:

3.6.2

3.6.3

Table 18. JTAG ID Register (Continued)

27:12

1:11

0

Manufacturer part number

Manufacturer ID

Mandatory JTAG field

0xae18

0x215

b1

Clocks

SerDes Clocks, RCK[A:B][1:4]P/N

The SerDes reference clocks are externally provided, low jitter,

differential CMOS/CML clocks in the range of 100MHz to 400MHz,

representing 1/10th the serial data rate. The requirements for these

inputs are given in Table 19.

Table 19. Reference Clock Requirements

Symbol

Description

VIL-RC

VIH-RC

JCLK-REF

TRRef, TFRef

Low-level CML/CMOS input voltage

High-level CML/CMOS input voltage

Clock frequency range

Duty cycle

Skew between + and – inputs of a single

reference clock

Input jitter (peak to peak)

Rise/Fall time of differential inputs

1) UI refers to the Bit Time period

2) RCUI refers to the Reference Clock period

Min

0

0

100

40

Typ

VDD

50

0.2

Max

VDD-0.5

400

60

.05

0.1

0.25

Units

V

V

MHz

%

RCUI

UI1

RCUI2

CPU Interface Clock

The clock source for the CPU interface on the FM2112 must meet the

following requirements:

• 3.3V CMOS drive

• Maximum frequency of 100 MHz.

JTAG Clock

The FM2112 supports JTAG. The clock source must meet the LVTTL

specification and:

• Duty cycle distortion of 40/60%, maximum

• Maximum frequency of 40 MHz

71

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