FBFM2112F897CSLJLS 查看數據表（PDF） - Intel

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FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.5.5.1

Mode=1: This mode selects operations compatible with a standard

octal shift register such as (74HC595). Data polarity is inverted.

The only difference between the 2 modes is the polarity of the data.

Both will cycle through a continuous 36b cycle pattern. The data for

each LED is placed serially on the appropriate data line and clocked out

by LED_CLK. See Table 16 for details on the sequence.

LED Clock Rate

This section provides information for setting the LED freq bits.

Setting these two bits to 0x0 will cause the CLK_LED to be CPU_CLK

rate divided by 4. This setting is there mainly for simulation purposes

and is not useful for device operation. The LED freq bits may be set to

values between 0x1 to 0x7F, corresponding to an LED divisor of 1 to

127. For those settings the LED clock rate will be the CPU clock divided

by (2^15 * divisor).

2^15 is about 33,000, so for a CPU clock of 33MHz, the LED clock

would be divided down to 1KHz with no other factor involved. If the

LED freq bits are set to 0x02, one would get 500Hz, or a period of 2

ms. Recall that each LED is signaled at 1/36th of this rate (the LED

frame rate - see the LED sequence table and LED timing diagram). This

would give a rate of about 14 Hz for each LED, which is appropriate

because the human eye will be able to detect the blinking LED state at

that rate.

Table 16. Port LED Sequence

Cycle

1

LED_Data0

Start Bit

LED_Data1

Start Bit

2:3

Pad Bits

Pad Bits

4:27

28:30

34:36

LED Data Bits

Port1 bits 0,1,2 …

Port8 bits 0,1,2

Port0 bits 0,1,2

Pad Bits

LED Data Bits

Port9 bits 0,1,2 …

Port16 bits 0,1,2

Pad bits

Pad Bits

LED_Data2

Start Bit

Pad Bits

LED Data Bits

Port17 bits 0,1,2 …

Port24 bits 0,1,2

Pad bits

Pad Bits

Description

Used to start the 48b

series. Will always be a

logical 1

Used as fillers in the data

stream to extend the

length to the required 36b

frame length. These bits

will always be logical 0.

Actual data to be

transmitted

Enable will be asserted

synchronously with bit 36

68

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