FBFM2112F897CSLJLS 查看數據表（PDF） - Intel

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FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.5.2.5

3.5.2.6

STEP 1: Taking management out of reset

• Deassert reset (note that both CHIP_RESET_N and EBI_RESET_N can be tied

together)

• Write 0xD04 into CHIP_MODE

• Poll BOOT_STATUS periodically until it goes to 0 (will be within few seconds)

• You can now read/write into any management register (read

VITAL_PRODUCT_DATA as an example

STEP 2: Programming PLL for Frame Processor

• Setup PLL_FH_CTRL as desired (depends on FH_REF_CLK value)

• Poll PLL_FH_STATUS to check it locks, it will normally locks in few microseconds

STEP 3: Enabling Frame Processor

• Write 0 into SOFT_RESET

• You can now read/write into any management register

STEP 4: Enabling Ports

• Setup correct reference clock for each port using PORT_CLK_SEL (writing 0 in this

register will set all ports to use refclk A)

• Take individual ports out of reset using PORT_RESET (writing 0 will take all ports

out of reset).

• Bring-up the serdes as follows:

— Apply power to all components, including the switch

— De-assert master reset on board

— Optional de-assert reset on the switch (but not required at this stage)

— Processor boots (if processor present)

— Processor de-assert reset on the switch (if not done)

—EBI clock must be present on the switch before the reset is deasserted (10

cycles are good enough).

Management Bus

The Management bus is used to read / write registers. Access to the

management bus is granted with the following precedence.

• BOOT FSM

• JTAG

• CPU Interface

Scan Chains Converter

The Scan Chain Converter is a management feature that converts

management requests into DFT scan chain requests to grant scan

access to the device from the CPU.

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