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STM32F051R4U7(2012) 查看數據表(PDF) - STMicroelectronics

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STM32F051R4U7 Datasheet PDF : 104 Pages
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Electrical characteristics
STM32F051x
6.3.16 DAC electrical specifications
Table 57. DAC characteristics
Symbol
Parameter
Min Typ
Max
Unit
Comments
VDDA
RLOAD(1)
Analog supply voltage for
DAC ON
2.4
Resistive load with buffer ON 5
RO(1)
Impedance output with buffer
OFF
-
CLOAD(1) Capacitive load
-
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer ON
0.2
DAC_OUT Higher DAC_OUT voltage
max(1)
with buffer ON
-
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer OFF
-
DAC_OUT Higher DAC_OUT voltage
max(1)
with buffer OFF
-
DAC DC current
-
IDDA
consumption in quiescent
mode (Standby mode)
-
-
3.6
V
-
-
kΩ Load is referred to ground
When the buffer is OFF, the Minimum
-
15
kΩ
resistive load between DAC_OUT
and VSS to have a 1% accuracy is
1.5 MΩ
Maximum capacitive load at
-
50
pF DAC_OUT pin (when the buffer is
ON).
It gives the maximum output
-
-
V excursion of the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VDDA = 3.6 V
-
VDDA – 0.2
V and (0x155) and (0xEAB) at VDDA =
2.4 V
0.5
-
mV
It gives the maximum output
excursion of the DAC.
- VDDA – 1LSB V
-
380
µA
With no load, middle code (0x800) on
the input
-
480
µA
With no load, worst code (0xF1C) on
the input
DNL(2)
Differential non linearity
Difference between two
consecutive code-1LSB)
-
-
-
-
Integral non linearity
(difference between
-
-
INL(2)
measured value at Code i
and the value at Code i on a
line drawn between Code 0 -
-
and last Code 1023)
Offset error
-
-
(difference between
Offset(2) measured value at Code
-
-
(0x800) and the ideal value =
VDDA/2)
-
-
Gain
error(2)
Gain error
-
-
±0.5
±2
±1
±4
±10
±3
±12
±0.5
LSB
Given for the DAC in 10-bit
configuration
LSB
Given for the DAC in 12-bit
configuration
LSB
Given for the DAC in 10-bit
configuration
LSB
Given for the DAC in 12-bit
configuration
mV
Given for the DAC in 12-bit
configuration
LSB
Given for the DAC in 10-bit at VDDA =
3.6 V
LSB
Given for the DAC in 12-bit at VDDA =
3.6 V
%
Given for the DAC in 12bit
configuration
80/105
Doc ID 022265 Rev 3

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