STM8S105K4T3(2015) 查看數據表（PDF） - STMicroelectronics

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STM8S105K4T3
(Rev.:2015)

Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbyte Flash, integrated EEPROM, 10-bit ADC, timers, UART, SPI, I²C

STMicroelectronics 

Electrical characteristics

STM8S105x4/6

10.3.10

I2C interface characteristics

Table 43. I2C characteristics

Symbol

Parameter

Standard mode I2C Fast mode I2C(1)

Unit

Min(2)

Max(2) Min(2) Max(2)

tw(SCLL)

tw(SCLH)

tsu(SDA)

th(SDA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

4.7

-

1.3

-

µs

4.0

-

0.6

-

250

-

100

-

0(3)

-

0(4)

900(3)

tr(SDA)

tr(SCL)

SDA and SCL rise time

(VDD = 3 to 5.5 V)

-

tf(SDA)

tf(SCL)

SDA and SCL fall time

(VDD = 3 to 5.5 V)

-

th(STA)

START condition hold time

4.0

tsu(STA)

Repeated START condition setup time

4.7

tsu(STO) STOP condition setup time

4.0

tw(STO:STA)

STOP to START condition time 

(bus free)

4.7

1000

300

-

-

-

-

-

300 ns

-

300

0.6

-

0.6

-

0.6

-

µs

1.3

-

Cb

Capacitive load for each bus line

-

400

-

400 pF

1. fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400 kHz)

2. Data based on standard I2C protocol requirement, not tested in production

3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low

time

4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL

Figure 44. Typical application with I2C bus and timing diagram

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