DSPIC33FJ32MC304-I/SP 查看數據表（PDF） - Microchip Technology

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DSPIC33FJ32MC304-I/SP

16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Motor Control PWM and Advanced Analog

Microchip Technology 

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04

18.3 SPI Control Registers

REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER

R/W-0

U-0

R/W-0

U-0

U-0

U-0

U-0

SPIEN

—

SPISIDL

—

—

—

—

bit 15

U-0

—

bit 8

U-0

R/C-0

U-0

U-0

U-0

—

SPIROV

—

—

—

bit 7

U-0

R-0

R-0

—

SPITBF

SPIRBF

bit 0

Legend:

R = Readable bit

-n = Value at POR

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

bit 14

bit 13

bit 12-7

bit 6

bit 5-2

bit 1

bit 0

SPIEN: SPIx Enable bit

1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins

0 = Disables module

Unimplemented: Read as ‘0’

SPISIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

Unimplemented: Read as ‘0’

SPIROV: Receive Overflow Flag bit

1 = A new byte/word is completely received and discarded. The user software has not read the

previous data in the SPIxBUF register

0 = No overflow has occurred

Unimplemented: Read as ‘0’

SPITBF: SPIx Transmit Buffer Full Status bit

1 = Transmit not yet started, SPIxTXB is full

0 = Transmit started, SPIxTXB is empty

Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB

Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR

SPIRBF: SPIx Receive Buffer Full Status bit

1 = Receive complete, SPIxRXB is full

0 = Receive is not complete, SPIxRXB is empty

Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB

Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB

© 2007-2012 Microchip Technology Inc.

DS70291G-page 235

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