DSPIC33FJ32MC304-I/SP 查看數據表（PDF） - Microchip Technology

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DSPIC33FJ32MC304-I/SP

16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Motor Control PWM and Advanced Analog

Microchip Technology 

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04

REGISTER 18-3: SPIxCON2: SPIx CONTROL REGISTER 2

R/W-0

R/W-0

R/W-0

U-0

U-0

U-0

FRMEN

SPIFSD

FRMPOL

—

—

—

bit 15

U-0

U-0

—

—

bit 8

U-0

—

bit 7

U-0

U-0

U-0

U-0

U-0

R/W-0

U-0

—

—

—

—

—

FRMDLY

—

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

bit 14

bit 13

bit 12-2

bit 1

bit 0

FRMEN: Framed SPIx Support bit

1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)

0 = Framed SPIx support disabled

SPIFSD: Frame Sync Pulse Direction Control bit

1 = Frame sync pulse input (slave)

0 = Frame sync pulse output (master)

FRMPOL: Frame Sync Pulse Polarity bit

1 = Frame sync pulse is active-high

0 = Frame sync pulse is active-low

Unimplemented: Read as ‘0’

FRMDLY: Frame Sync Pulse Edge Select bit

1 = Frame sync pulse coincides with first bit clock

0 = Frame sync pulse precedes first bit clock

Unimplemented: This bit must not be set to ‘1’ by the user application

DS70291G-page 238

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