STM32F373VC(2013) 查看數據表（PDF） - STMicroelectronics

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STM32F373VC
(Rev.:2013)

ARM Cortex-M4 32b MCU+FPU, up to 256KB Flash+32KB SRAM timers, 4 ADCs (12/16-bit), 3 DACs, 2 comp., 2.0-3.6 V operation

STMicroelectronics 

Electrical characteristics

STM32F37xxx

2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should

be avoided as this significantly reduces the accuracy of the conversion being performed on another analog

input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject

negative currents.

Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not

affect the ADC accuracy.

3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.

4. Data based on characterization results, not tested in production.

Figure 29. ADC accuracy characteristics

4095

4094

4093

7

6

5

EO

4

3

2

1

EG

(2)

ET

(3)

(1)

EL

ED

1 LSBIDEAL

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

ET=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

EO=Offset Error: deviation between the first actual

transition and the first ideal one.

EG=Gain Error: deviation between the last ideal

transition and the last actual one.

ED=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

EL=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

0

1 2345 67

VSSA

4093 4094 4095 4096

VDDA

MS19880V1

Figure 30. Typical connection diagram using the ADC

RSRC(1)

AINx

7SRC

Cparasitic

VDD

VT

0.6 V

VT

0.6 V

IL±1 μA

Sample and hold ADC

converter

RADC(1)

12-bit

converter

CADC(1)

MS32163V1

1. Refer to Table 60 for the values of RSRC, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy

this, fADC should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 9. The 10 nF capacitor

should be ceramic (good quality) and it should be placed as close as possible to the chip.

100/131

DocID022691 Rev 4

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