STM32F373VC(2013) 查看數據表（PDF） - STMicroelectronics

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STM32F373VC
(Rev.:2013)

ARM Cortex-M4 32b MCU+FPU, up to 256KB Flash+32KB SRAM timers, 4 ADCs (12/16-bit), 3 DACs, 2 comp., 2.0-3.6 V operation

STMicroelectronics 

Electrical characteristics

STM32F37xxx

6.3.17

Note:

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 60 are preliminary values derived

from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply

voltage conditions summarized in Table 22.

It is recommended to perform a calibration after each power-up.

Table 60. ADC characteristics

Symbol

Parameter

Conditions

Min

Typ Max Unit

VDDA Power supply

VREF+ Positive reference voltage

IDDA(ADC)(1) Current consumption from VDDA VDD = VDDA = 3.3 V

IVREF Current on the VREF input pin

fADC

fS(3)

ADC clock frequency

Sampling rate

fTRIG(3) External trigger frequency

fADC = 14 MHz

2.4

2.4

-

-

0.6

0.05

-

-

-

-

0.9

160(2)

-

-

-

-

3.6

VDDA

-

220(2)

14

1

823

17

VAIN Conversion voltage range

0 (VSSA or VREF-

tied to ground)

-

VREF+

RSRC(3) Signal source impedance

See Equation 1 and

Table 61 for details

-

RADC(3) Sampling switch resistance

-

CADC(3)

Internal sample and hold

capacitor

-

-

50

-

1

-

8

tCAL(3) Calibration time

fADC = 14 MHz

5.9

83

tlat(3)

Injection trigger conversion

latency

fADC = 14 MHz

-

-

- 0.214

-

2(4)

tlatr(3)

Regular trigger conversion

latency

fADC = 14 MHz

-

-

- 0.143

-

2(4)

tS(3)

Sampling time

tSTAB(3) Power-up time

tCONV(3)

Total conversion time (including

sampling time)

fADC = 14 MHz

fADC = 14 MHz

0.107

-

17.1

1.5

- 239.5

0

0

1

1

-

18

14 to 252 (tS for sampling +12.5 for

successive approximation)

V

V

mA

µA

MHz

MHz

kHz

1/fADC

V

κΩ

κΩ

pF

µs

1/fADC

µs

1/fADC

µs

1/fADC

µs

1/fADC

µs

µs

1/fADC

1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA

on IDD is present

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 60

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