STM32F373VC(2013) 查看數據表（PDF） - STMicroelectronics
零件编号
产品描述 (功能)
生产厂家
STM32F373VC
(Rev.:2013)
(Rev.:2013)
STMicroelectronics
STM32F373VC Datasheet PDF : 131 Pages
| |||
Electrical characteristics
STM32F37xxx
Symbol
Table 63. DAC characteristics (continued)
Parameter
Min Typ
Max
Unit
Comments
Offset error
-
-
(difference between
Offset(3) measured value at Code
-
-
(0x800) and the ideal value
= VREF+/2)
-
-
Gain
error(3)
Gain error
-
-
Settling time (full scale: for
a 10-bit input code
tSETTLING( transition between the
3)
lowest and the highest input
-
3
codes when DAC_OUT
reaches final value ±1LSB
Max frequency for a correct
Update
rate(3)
DAC_OUT change when
small variation in the input
code (from code i to
-
-
i+1LSB)
Wakeup time from off state
tWAKEUP(3) (Setting the ENx bit in the
- 6.5
DAC Control register)
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
- -67
measurement
±10
mV
±3
LSB
Given for the DAC in 10-bit at VREF+
= 3.6 V
±12
LSB
Given for the DAC in 12-bit at VREF+
= 3.6 V
±0.5
%
Given for the DAC in 12bit
configuration
4
µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
1
MS/
s
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
10
µs input code between lowest and
highest possible ones.
-40
dB No RLOAD, CLOAD = 50 pF
1. Guaranteed by design, not tested in production.
2. Quiescent mode refers to the state of the DAC keeping a steady value on the output, so no dynamic consumption is
involved.
3. Guaranteed by characterization, not tested in production.
Figure 31. 12-bit buffered /non-buffered DAC
12-bit
digital to
analog
converter
Buffer(1)
DACx_OUT
R LOAD
C LOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
102/131
DocID022691 Rev 4
Share Link: 