Electrical characteristics
STM32F37xxx
Table 69. IWDG min/max timeout period at 40 kHz (LSI) (continued)(1)(2)
Prescaler divider PR[2:0] bits
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
/32
3
0.8
/64
4
1.6
/128
5
3.2
/256
7
6.4
3276.8
6553.6
13107.2
26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
2. Data based on characterization results, not tested in production.
Table 70. WWDG min-max timeout value @72 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
1
0
0.05687
3.6409
2
1
0.1137
7.2817
4
2
8
3
0.2275
0.4551
14.564
29.127
106/131
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