DSPIC33FJ16GS102-I/SO 查看數據表（PDF） - Microchip Technology

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DSPIC33FJ16GS102-I/SO

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

TABLE 21-2: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field

Register

Description

FWDTEN

WINDIS

WDTPRE

WDTPOST<3:0>

FPWRT<2:0>

JTAGEN

ICS<1:0>

FWDT

FWDT

FWDT

FWDT

FPOR

FICD

FICD

Watchdog Timer Enable bit

1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled;

clearing the SWDTEN bit in the RCON register will have no effect)

0 = Watchdog Timer enabled/disabled by user software (LPRC can be

disabled by clearing the SWDTEN bit in the RCON register)

Watchdog Timer Window Enable bit

1 = Watchdog Timer in Non-Window mode

0 = Watchdog Timer in Window mode

Watchdog Timer Prescaler bit

1 = 1:128

0 = 1:32

Watchdog Timer Postscaler bits

1111 = 1:32,768

1110 = 1:16,384

•

•

•

0001 = 1:2

0000 = 1:1

Power-on Reset Timer Value Select bits

111 = PWRT = 128 ms

110 = PWRT = 64 ms

101 = PWRT = 32 ms

100 = PWRT = 16 ms

011 = PWRT = 8 ms

010 = PWRT = 4 ms

001 = PWRT = 2 ms

000 = PWRT = Disabled

JTAG Enable bit

1 = JTAG is enabled

0 = JTAG is disabled

ICD Communication Channel Select Enable bits

11 = Communicate on PGEC1 and PGED1

10 = Communicate on PGEC2 and PGED2

01 = Communicate on PGEC3 and PGED3

00 = Reserved, do not use.

© 2009 Microchip Technology Inc.

Preliminary

DS70318D-page 265

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