DSPIC33FJ16GS102-I/SO 查看數據表（PDF） - Microchip Technology

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DSPIC33FJ16GS102-I/SO

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

21.4 Watchdog Timer (WDT)

For

dsPIC33FJ06GS101/X02

and

dsPIC33FJ16GSX02/X04 devices, the WDT is driven by

the LPRC oscillator. When the WDT is enabled, the clock

source is also enabled.

21.4.1 PRESCALER/POSTSCALER

The nominal WDT clock source from LPRC is 32 kHz.

This feeds a prescaler than can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the WDTPRE Configuration bit.

With a 32 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5-bit mode, or

4 ms in 7-bit mode.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPOST<3:0>

Configuration bits (FWDT<3:0>) which allow the

selection of 16 settings, from 1:1 to 1:32,768. Using the

prescaler and postscaler, time-out periods ranging from

1 ms to 131 seconds can be achieved.

The WDT, prescaler and postscaler are reset:

• On any device Reset

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAV instruction is executed

(i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

• By a CLRWDT instruction during normal execution

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

FIGURE 21-2:

WDT BLOCK DIAGRAM

All Device Resets

Transition to New Clock Source

Exit Sleep or Idle Mode

PWRSAV Instruction

CLRWDT Instruction

SWDTEN

FWDTEN

LPRC Clock

WDTPRE

RS

Prescaler

(Divide by N1)

21.4.2 SLEEP AND IDLE MODES

If the WDT is enabled, it will continue to run during

Sleep or Idle modes. When the WDT time-out occurs,

the device will wake the device and code execution will

continue from where the PWRSAV instruction was

executed. The corresponding SLEEP or IDLE bits

(RCON<3:2>) will need to be cleared in software after

the device wakes up.

21.4.3 ENABLING WDT

The WDT is enabled or disabled by the FWDTEN

Configuration bit in the FWDT Configuration register.

When the FWDTEN Configuration bit is set, the WDT is

always enabled.

The WDT can be optionally controlled in software when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN

control bit is cleared on any device Reset. The software

WDT option allows the user application to enable the

WDT for critical code segments and disable the WDT

during non-critical segments for maximum power

savings.

Note:

If the WINDIS bit (FWDT<6>) is cleared, the

CLRWDT instruction should be executed by

the application software only during the last

1/4 of the WDT period. This CLRWDT

window can be determined by using a timer.

If a CLRWDT instruction is executed before

this window, a WDT Reset occurs.

The WDT flag bit, WDTO (RCON<4>), is not automatically

cleared following a WDT time-out. To detect subsequent

WDT events, the flag must be cleared in software.

Watchdog Timer

WDTPOST<3:0>

RS

Postscaler

(Divide by N2)

Sleep/Idle

1

0

WDT

Wake-up

WDT

Reset

WINDIS

WDT Window Select

CLRWDT Instruction

© 2009 Microchip Technology Inc.

Preliminary

DS70318D-page 267

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