DSPIC33FJ32GP802-I/SP 查看數據表（PDF） - Microchip Technology

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DSPIC33FJ32GP802-I/SP

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

REGISTER 19-1: CiCTRL1: ECAN™ CONTROL REGISTER 1

U-0

—

bit 15

U-0

R/W-0

R/W-0

r-0

—

CSIDL

ABAT

—

R/W-1

R/W-0

REQOP<2:0>

R/W-0

bit 8

R-1

R-0

R-0

OPMODE<2:0>

bit 7

U-0

R/W-0

U-0

—

CANCAP

—

U-0

R/W-0

—

WIN

bit 0

Legend:

R = Readable bit

-n = Value at POR

r = Bit is reserved

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-14

bit 13

bit 12

bit 11

bit 10-8

bit 7-5

bit 4

bit 3

bit 2-1

bit 0

Unimplemented: Read as ‘0’

CSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

ABAT: Abort All Pending Transmissions bit

1 = Signal all transmit buffers to abort transmission.

0 = Module will clear this bit when all transmissions are aborted

Reserved: Do not use

REQOP<2:0>: Request Operation Mode bits

000 = Set Normal Operation mode

001 = Set Disable mode

010 = Set Loopback mode

011 = Set Listen Only Mode

100 = Set Configuration mode

101 = Reserved

110 = Reserved

111 = Set Listen All Messages mode

OPMODE<2:0>: Operation Mode bits

000 = Module is in Normal Operation mode

001 = Module is in Disable mode

010 = Module is in Loopback mode

011 = Module is in Listen Only mode

100 = Module is in Configuration mode

101 = Reserved

110 = Reserved

111 = Module is in Listen All Messages mode

Unimplemented: Read as ‘0’

CANCAP: CAN Message Receive Timer Capture Event Enable bit

1 = Enable input capture based on CAN message receive

0 = Disable CAN capture

Unimplemented: Read as ‘0’

WIN: SFR Map Window Select bit

1 = Use filter window

0 = Use buffer window

DS70292D-page 224

Preliminary

 2009 Microchip Technology Inc.

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