DSPIC33FJ32GP802-I/SP 查看數據表（PDF） - Microchip Technology
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DSPIC33FJ32GP802-I/SP Datasheet PDF : 402 Pages
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dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-7: CiINTE: ECAN™ INTERRUPT ENABLE REGISTER
U-0
—
bit 15
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
bit 8
R/W-0
IVRIE
bit 7
R/W-0
WAKIE
R/W-0
ERRIE
R/W-0
—
R/W-0
FIFOIE
R/W-0
RBOVIE
R/W-0
RBIE
R/W-0
TBIE
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Writable bit, but only ‘0’ can be written to clear the bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
IVRIE: Invalid Message Received Interrupt Enable bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
WAKIE: Bus Wake-up Activity Interrupt Flag bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
ERRIE: Error Interrupt Enable bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
Unimplemented: Read as ‘0’
FIFOIE: FIFO Almost Full Interrupt Enable bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
RBOVIE: RX Buffer Overflow Interrupt Enable bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
RBIE: RX Buffer Interrupt Enable bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
TBIE: TX Buffer Interrupt Enable bit
1 = Interrupt Request Enabled
0 = Interrupt Request not enabled
DS70292D-page 230
Preliminary
2009 Microchip Technology Inc.
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