STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
Table 35. Synchronous multiplexed PSRAM write timings(1)(2)
Symbol
Parameter
Min
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_Nex low (x = 0...2)
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
td(CLKL-Data)
FSMC_A/D[15:0] valid after FSMC_CLK low
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
td(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high
1. CL = 15 pF.
2. Preliminary values
27.7
2
5
2
1
3
7
2
1
Max Unit
ns
2
ns
ns
4
ns
ns
0
ns
ns
1
ns
ns
12
ns
ns
6
ns
ns
ns
ns
Doc ID 15081 Rev 7
63/98