STM32F100ZD 查看數據表（PDF） - STMicroelectronics

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STM32F100ZD

High-density value line, advanced ARM-based 32-bit MCU with 256 to 512 KB Flash, 16 timers, ADC, DAC & 11 comm interfaces

STMicroelectronics 

STM32F100xC, STM32F100xD, STM32F100xE

Electrical characteristics

Table 51. ADC characteristics

Symbol

Parameter

Conditions

Min

Typ Max Unit

VDDA

VREF+

IVREF

fADC

fS(2)

Power supply

Positive reference voltage

Current on the VREF input

pin

ADC clock frequency

Sampling rate

fTRIG(2) External trigger frequency

VAIN(3) Conversion voltage range

fADC = 12 MHz

2.4

3.6

V

2.4

VDDA

V

160(1) 220(1)

µA

0.6

0.05

0 (VSSA tied to

ground)

12

1

823

17

VREF+

MHz

MHz

kHz

1/fADC

V

RAIN(2) External input impedance

RADC(2) Sampling switch resistance

CADC(2)

Internal sample and hold

capacitor

tCAL(2) Calibration time

tlat(2)

Injection trigger conversion

latency

tlatr(2)

Regular trigger conversion

latency

tS(2) Sampling time

tSTAB(2) Power-up time

tCONV(2)

Total conversion time

(including sampling time)

See Equation 1 and

Table 52 for details

fADC = 12 MHz

fADC = 12 MHz

fADC = 12 MHz

fADC = 12 MHz

fADC = 12 MHz

50

kΩ

1

kΩ

8

pF

5.9

83

0.214

3(4)

0.143

2(4)

0.125

17.1

1.5

239.5

0

0

1

1.17

21

14 to 252 (tS for sampling +12.5 for

successive approximation)

µs

1/fADC

µs

1/fADC

µs

1/fADC

µs

1/fADC

µs

µs

1/fADC

1. Preliminary values.

2. Guaranteed by design, not tested in production.

3. VREF+ is internally connected to VDDA

4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 51.

EqRuAaItNio<n-f-A-1---D:---C-R---×-A----I-CN-----Am---D--T-aC---Sx--×---f--o-l-n--r--m(---2--u-N---l-+-a---2:---) – RADC

The above formula (Equation 1) is used to determine the maximum external impedance allowed for an

error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Doc ID 15081 Rev 7

81/98

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