STM32F100ZD 查看數據表（PDF） - STMicroelectronics
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STM32F100ZD Datasheet PDF : 98 Pages
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STM32F100xC, STM32F100xD, STM32F100xE
Electrical characteristics
5.3.19 DAC electrical specifications
Table 55. DAC characteristics
Symbol
Parameter
Min Typ Max(1) Unit
Comments
VDDA
Analog supply voltage
2.4
VREF+
Reference supply voltage
2.4
VSSA
Ground
0
RLOAD(1) Resistive load with buffer ON
5
RO(1)
Impedance output with buffer OFF
CLOAD(1) Capacitive load
DAC_OUT Lower DAC_OUT voltage with buffer
min(1)
ON
0.2
DAC_OUT Higher DAC_OUT voltage with buffer
max(1)
ON
DAC_OUT Lower DAC_OUT voltage with buffer
min(1)
OFF
0.5
DAC_OUT Higher DAC_OUT voltage with buffer
max(1)
OFF
IDDVREF+
DAC DC current consumption in
quiescent mode (Standby mode)
IDDA
DAC DC current consumption in
quiescent mode (2)
3.6
V
3.6
V
0
V
kΩ
15
kΩ
50
pF
V
VDDA –
0.2
V
VREF+ must always be below
VDDA
When the buffer is OFF, the
Minimum resistive load
between DAC_OUT and VSS to
have a 1% accuracy is 1.5 MΩ
Maximum capacitive load at
DAC_OUT pin (when the buffer
is ON).
It gives the maximum output
excursion of the DAC.
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
VREF+ = 3.6 V and (0x155) and
(0xEAB) at VREF+ = 2.4 V
mV
VREF+
– 1LSB
V
220 µA
380 µA
480 µA
It gives the maximum output
excursion of the DAC.
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
With no load, middle code
(0x800) on the inputs
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
DNL(1)
Differential non linearity Difference
between two consecutive code-1LSB)
INL(1)
Integral non linearity (difference
between measured value at Code i
and the value at Code i on a line
drawn between Code 0 and last Code
1023)
±0.5
±2
±1
±4
LSB
Given for the DAC in 10-bit
configuration
LSB
Given for the DAC in 12-bit
configuration
LSB
Given for the DAC in 10-bit
configuration
LSB
Given for the DAC in 12-bit
configuration
Doc ID 15081 Rev 7
85/98
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