PSD4211F3V-70UI 查看數據表（PDF） - STMicroelectronics

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PSD4211F3V-70UI

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

STMicroelectronics 

PSD4235G2

Figure 16. Input Macrocell

INTERNAL DATA BUS

ENABLE (.OE)

INPUT MACROCELL _ RD

OUTPUT

PT

MACROCELLS A

AND

MACROCELLS B

DIRECTION

REGISTER

PT

PORT

DRIVER

I/O PIN

FEEDBACK

MUX

QD

D FF

QD

G

LATCH

PT

MUX ALE/AS

INPUT MACROCELL

AI04926

External Chip Select. The CPLD also provides

eight External Chip Select (ECS0-ECS7) outputs

that can be used to select external devices. Each

External Chip Select (ECS0-ECS7) consists of

one product term that can be configured active

High or Low.

The output enable of the pin is controlled by either

the output enable product term or the Direction

Register. (See Figure 17.)

Figure 17. External Chip Select Signal

38/89

Port C or Port F

ENABLE (.OE) PT

DIRECTION

REGISTER

ECS PT

POLARITY

BIT

ECS

To Port C or F

PORT PIN

AI04927

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